The video discusses Intel’s upcoming Xeon 7 processor, codenamed Diamond Rapids, which is set to launch in 2027 and will power data centers for AI and enterprise workloads. The presenter reviews Intel’s Hot Chips presentation, highlighting the evolution of Intel’s Xeon interconnect architectures from ring topologies in older generations to mesh designs in Skylake and Cascade Lake, and then to chiplet-based designs in Sapphire Rapids and Emerald Rapids. Diamond Rapids introduces a new fan-out fabric architecture that centralizes memory, IO, and accelerators in fabric hubs, connecting multiple compute building blocks that contain core chiplets and shared last-level cache.
Each compute building block in Diamond Rapids can house up to four core chiplets, with each chiplet containing 16 cores, totaling up to 64 cores per building block. The base tile underneath these chiplets holds the shared last-level cache, with up to 320 MB per building block and a total of 1.2 GB across the chip. The fabric hubs manage memory channels, IO lanes, and accelerators, supporting DDR5 memory up to DDR5-8000 speeds, PCIe Gen 6 with CXL 3, and UPI 3 for socket-to-socket communication. The chiplets are manufactured using Intel’s advanced process nodes, including Intel 3 and 18A, with hybrid bonding packaging technology (Foveros 3D Direct) used to connect core chiplets to base tiles.
Diamond Rapids features significant improvements in power and thermal management, including distinct voltage and frequency domains for different chiplets, new low-power idle states with L2 cache retention, and priority turbo cores for enhanced performance. The architecture supports advanced performance extensions (APX) that add new instructions and increase the number of general-purpose registers to 32, improving performance with minimal code changes. Security enhancements include improved RAS features, memory encryption, and better cache coherence mechanisms.
The chip’s scalability is a key focus, with the ability to configure different numbers of compute building blocks and core chiplets to target various market segments, from high-core-count server SKUs to specialized low-core, high-frequency variants for niche applications like high-frequency trading. While the current details focus on performance cores (P-cores), the presenter notes that information about efficiency cores (E-cores) in Diamond Rapids is still unknown. The chip is expected to have a TDP in the range of previous high-end Xeons, around 450-500 watts.
Finally, the presenter speculates on future developments, including potential NVLink support through Nvidia partnerships and the next-generation Coral Rapids processor. Diamond Rapids represents a significant step forward in Intel’s data center CPU architecture, emphasizing modularity, scalability, and advanced interconnects to meet the growing demands of AI and enterprise workloads. The video concludes by inviting viewers to share their thoughts and mentions merchandise related to the channel.
